This is a placeholder post — the structure and styling are real, the words are a stand-in until I write the actual thing.
The first thing that surprised me about wafer-scale was how little of the engineering is about making a perfect wafer. Nobody expects a perfect wafer. The whole architecture is built on the assumption that some fraction of cores will be dead on arrival, and the job of the system is to route around them without the user ever noticing.
Quantum hardware is not there yet. We still talk about qubit counts the way we once talked about transistor counts, as if every one of them works. The honest version of the number is much smaller, and the interesting engineering question is what you do about the gap.
Three moves that transfer
There are three moves that transfer directly from classical wafer-scale:
- Redundancy at the tile level — build more than you need and expect to lose some.
- A mapping layer that knows which physical resources are actually usable.
- A bringup flow that discovers that map cheaply, every time.
None of them are exotic. All of them are unglamorous infrastructure work that determines whether the machine ships.
The part that doesn’t transfer
A dead core is static and a bad qubit is not. Coherence drifts. A qubit that calibrated well this morning may be the worst one on the chip by evening. So the mapping layer cannot be a one-time bringup artifact; it has to be a running service.
Which brings me back to the thing I keep writing about: the bottleneck is rarely the physics. It is the tooling around the physics, and the willingness to treat yield as a design input rather than a manufacturing embarrassment.