Systems I've designed and shipped across AI silicon and quantum computing — from production bringup tooling to open research artifacts.
Monte Carlo methods identify superconducting device parameters that stay robust under real fabrication variance, and GDS layout generation takes the chosen design straight to mask. Built because a device that only works at nominal parameters is a hypothesis, not a device.
A decoder with explicit latency and accuracy tiers: a fast hardware path handles the common local cases, a slower path corrects the record behind it. Architected for acceleration rather than for a software benchmark.
Python and shell tooling that takes a fresh wafer from power-on to a full performance characterization report. Now part of the standard bringup path for every system that leaves the floor.
Programming and behavioural analysis tooling for the largest chip in production. Used daily across the bringup team to isolate failures that only appear at full wafer scale.
Cross-functional enablement of a thermal stress mode that pushes a whole system to worst-case load, exposing power and thermal failures that nominal testing never reached.
A 14+ layer PCB validating I2C, SPI, UART, I2S, MIPI and LPDP on Apple R1 silicon — owned end to end from schematic capture through layout, bringup and characterization.
Python and TCL tooling that generated validation board schematic drawings from a netlist description, collapsing a one-to-two week task into an hour.
Verilog for Xilinx Spartan and Zynq parts, unlocking validation paths on Mac and phone silicon that the SoC alone could not expose.
Perfstate transition and inrush current analysis across the PCB–SoC boundary, feeding measured behaviour back into power delivery network design.
Functional and PVT characterization of ADC and NAFLL modules on the Turing GPU, with noise measurement automated end to end.
An electro-mechanical system that moves SoCs between development boards, taking humans out of the characterization loop entirely.
Co-authored technical report on test point insertion strategy for improved fault coverage. Second place at the Synopsys Users Group conference.