Product Engineer Nov 2023 — Present
Cerebras Systems — Built the wafer bringup flow — Python and shell tooling that characterizes system performance end to end. — Designed Python debug tools to program and analyze the behaviour of the Wafer Scale Engine. — Enabled heater-mode support with cross-functional teams for whole-system stress testing.
Silicon Validation Hardware Engineer Jun 2020 — Oct 2023
Apple, Inc. — Owned the entire design flow for 14+ layer PCBs used for SoC characterization and feature validation. — Wrote Verilog for Xilinx Spartan and Zynq SoCs to unlock validation features on Mac and phone silicon. — Designed the board validating I2C, SPI, UART, I2S, MIPI and LPDP interfaces on the Apple R1 SoC. — Automated schematic drawing generation in Python and TCL, cutting development from 1–2 weeks to 1 hour. — Characterized perfstate transitions and inrush behaviour across the PCB–SoC power delivery network.
Silicon Solutions Engineering Intern May — Aug 2018
NVIDIA Corporation — Performed functional and PVT characterization of ADC and NAFLL modules on the Turing GPU. — Automated noise measurement and SoC characterization in Python and JavaScript. — Built an electro-mechanical system to swap SoCs between development boards.
Digital Hardware Designer Jan — Apr 2017
Cognitive Systems Corp. — Modified ASIC module I/O in Java and Synopsys VCS to reduce critical path slack across clocks. — Built a CI-backed analytics tool visualizing ASIC module build data. — Co-authored a test point insertion report — second place at the Synopsys Users Group conference.